1. Field of the Invention
The present invention relates to a semiconductor device comprising a through electrode and method for manufacturing thereof.
2. Related Art
In recent years, semiconductor chips (hereinafter referred to as simply “chips”) having very large scale integrated circuit (VLSI) are frequently employed for forming critical portions in computers and communication devices. A structure of forming a multi-layered component by forming a plurality of chips or a structure of coupling the chips to the interconnect board via a flip-chip coupling is often employed among the usages of such chips. A technique for providing an electrical conduction between the front side and back side of the chip is critical, in the case that a plurality of chips are employed to form a multi-layered component or the chip is flip-chip coupled. Conventional semiconductor devices comprising through electrodes that provide an electrical conduction between the front side and back side of the chip are described in, for example, Japanese Patent Laid-Open No. 1998-223,833 (H10-223,833) , Japanese Patent Laid-Open No. 2002-170,904, Japanese Patent Laid-Open No. 2002-289,623 and Japanese Patent Laid-Open No. 2002-43,502.
Japanese Patent Laid-Open No. 1998-223,833 describes a method for electrically coupling a main face to a back face of a chip by forming a coupling plug consisting of a metal in the semiconductor substrate having elements collectively formed on the surface thereof. The coupling plug is composed of a metal plug disposed in a through hole and an insulating film interposed between the metal plug and the side wall of the through hole.
Japanese Patent Laid-Open No. 2002-170,904 describes a method for forming a through hole and a through electrode in the case that a chip is coupled via a chip size packaging (CSP) to form a multi-layered component. In the method described in Japanese Patent Laid-Open No. 2002-170,904, active elements or passive elements are collectively formed in the wafer level, and through holes for through electrodes are provided after a passivation layer is formed. The manufacturing of the through electrode is performed as follows. To form the through hole, a resist is applied on the entire face of the wafer, and the formed resist is partially removed to form openings using a photolithography technique, and then a dry etching or a wet etching is performed to form openings on the semiconductor substrate. Then, a seed layer is formed, and the photolithography technique is performed again, and then an electrolytic plating is performed.
Japanese Patent Laid-Open No. 2002-289,623 describes a method for providing a duplex insulation for a through electrode, for the purpose of preventing an insulation defect or a coupling defect to improve a connecting reliability. In such method, a narrow slit is provided so as to surround a section of the through electrode in a circumference of an opening having the through electrode disposed therein, when the semiconductor substrate is etched to form the through hole, and then the slit is completely filled using a process for coating with an insulating film for insulating the through electrode. The thickness of the semiconductor substrate is thinned until a bottom end of the slit is exposed in the process for thinning the film thickness, to form a semiconductor region electrically insulated from the substrate on the outside of the through electrode.
Japanese Patent Laid-Open No. 2002-43,502 describes a chip for a semiconductor device having an electrically insulated ring-type or annular Cu chip through plug. The ring-type Cu chip through plug is formed by forming a ring-shaped concave portion so that a convex Si wafer is remained therein, providing a Cu film on an insulating film covering each of the side faces and a bottom face of the concave portion, and filling the concave portion by performing an electrolytic plating technique from an origin of the Cu film. Japanese Patent Laid-Open No. 2002-43,502 also describes a configuration for forming a duplex slit via by a process, in which, the filling is not completed when a ring-shaped slit via is filled with Cu, and then slits of remained gaps are filled with an insulating material. It is described that the time required for filling the plug can be reduced by providing a ring-shaped geometry for the Cu chip through plug, as compared with the case of filling the circular concave portion.